This invention generally relates to measuring the thicknesses of capacitors formed in integrated circuits such as MOSFETs.
As MOSFETs continue to shrink in size laterally, it is also necessary to scale the gate dielectric thickness. Reliability concerns then limit the maximum voltages which can be placed across these thinner gate dielectrics. For today""s 0.15 um technologies and beyond, dielectric reliability often limits the performance which can be achieved by limiting the voltage at which the circuit can operate.
As an example, the maximum voltage which can be reliably placed across a typical gate oxide is calculated by limiting the maximum electric field to xe2x88x925 MV/cm across the thinnest oxide allowed by the process specification (usually 90% of the nominal oxide thickness). For example, for a 0.15 um DRAM technology, the array FET may have a gate oxide thickness of 5.5xc2x10.5 nm. The maximum permissible word line (gate) voltage is 2.60 V, which ensures that a 5.0 nm thick oxide will meet the reliability criteria. If we could electronically detect that the oxide thickness is 5.5 nm, then we could actually increase the WL voltage by 10% to 2.86 V and still guarantee reliability.
An object of this invention is to provide a circuit that outputs a voltage that is proportional to a MOS capacitor""s gate dielectric thickness.
Another object of the present invention is to provide a circuit that may be used both to output a voltage that is proportional to a MOS capacitor""s gate dielectric thickness, and to maintain a minimum electric field for thin gate oxides.
These and other objectives are attained with a method of measuring a capacitor gate dielectric thickness, comprising the steps of providing a circuit including a gate dielectric capacitor, said capacitor having a thickness; charging said circuit with a known current; and measuring a voltage output from said circuit, said voltage being proportional to said gate dielectric capacitor thickness.
The present invention may be effectively employed to obtain a number of important advantages. First, because the supply voltage scales with gate dielectric thickness, chip performance is maximized, even when gate oxide runs thick. Furthermore, oxide reliability is not affected because a constant electric field is guaranteed.
This invention may be employed to obtain performance improvements (i.e., maintaining the maximum reliable electric field for thick gate oxides). However, this circuit can also be used to maintain a minimum electric field for thin gate oxides. For chips which are not limited by performance, maintaining the minimum electric field will improve yield by reducing burn-in fallout and also reduce field failure rates.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.